Verification Techniques for System-Level Design

Verification Techniques for System-Level Design
Publisher: Morgan Kaufmann | ISBN: 0123706165 | edition 2007 | PDF | 256 pages | 2 mb

This book will explain how to verify SoC logic designs using "formal" and "semi-formal" verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in "functional" verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been getting much more attention.
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